The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have produced generations of semiconductor devices where each generation has smaller and more complex circuits than the previous generation. In the course of integrated circuit (IC) evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. But these advances have also increased the complexity of processing and manufacturing semiconductor devices.
For example, as device geometry shrinks, parasitic capacitance increases between interconnects such as source/drain (S/D) contact plugs and nearby gates. The increased parasitic capacitance degrades device performance. To lower parasitic capacitance, insulating materials with a relatively low dielectric constant (k), such as low-k dielectrics and air gaps, have been used between S/D features and nearby gates. But these materials have proven difficult to fabricate. In some instances, low-k dielectric materials are brittle, unstable, difficult to deposit, or sensitive to processes such as etching, annealing, and polishing, and air gap formations are difficult to control. For these reasons and others, it is desirable to improve the fabrication techniques of dielectrics between interconnects in order to reduce the parasitic capacitance while maintaining a high overall transistor density in IC.